Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- 3.3V Output Rise/Fall Time Diagram
- 2.5V Output Rise/Fall Time Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Differential Clock Input Interface
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
1
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
G
ENERAL
D
ESCRIPTION
T h e I C S 8 3 0 21I i s a 1 - t o - 1 Differential-to-
LVCMOS/LVTTL Translator and a member of the
HiPerClockSTM
family of High Perfor mance
Clock Solutions from ICS. The differential input
is highly flexible and can accept the following
input types: LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The
small 8-lead SOIC footprint makes this device ideal for use in
applications with limited board space.
F
EATURES
1 LVCMOS / LVTTL output
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 350MHz (typical)
Part-to-part skew: 500ps (maximum)
Small 8 lead SOIC package saves board space
Full 3.3V, 2.5V operating supply
-40C to 85C ambient operating temperature
Pin-to-pin compatible with MC100EPT21
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS83021I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
nc
CLK
nCLK
nc
1
2
3
4
Q0
CLK
nCLK
HiPerClockSTM
ICS
V
DD
Q0
nc
GND
8
7
6
5
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
2
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
3
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
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DD
= 3.3V0.3V or 2.5V5%, T
A
= -40C
TO
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AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
4
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V0.3V, T
A
= -40C
TO
85C
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83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
5
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
tsk(pp)
V
DD
2
V
DD
2
Qx
Qy
PART 1
PART 2
nCLK
CLK
Q0
t
PD
V
DD
2
-1.65V 0.15V
1.65V 0.15V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
Q0
GND
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V O
UTPUT
R
ISE
/F
ALL
T
IME
V
DD
SCOPE
Qx
LVCMOS
-1.25V 5%
1.25V 5%
GND
V
DD
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
6
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
7
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
F
IGURE
2C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
2A.
H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
2E.
H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
8
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
RANSISTOR
C
OUNT
The transistor count for ICS83021I is: 416
T
ABLE
5.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
9
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
ABLE
6. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
P
ACKAGE
O
UTLINE
- S
UFFIX
M
FOR
8 L
EAD
SOIC
L
O
B
M
Y
S
s
r
e
t
e
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i
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M
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
8
A
5
3
.
1
5
7
.
1
1
A
0
1
.
0
5
2
.
0
B
3
3
.
0
1
5
.
0
C
9
1
.
0
5
2
.
0
D
0
8
.
4
0
0
.
5
E
0
8
.
3
0
0
.
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e
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I
S
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83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
10
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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e
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
83021AMI
www.icst.com/products/hiperclocks.html
REV. B JUNE 30, 2004
11
Integrated
Circuit
Systems, Inc.
ICS83021I
1-
TO
-1
2.5V, 3.3V D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL T
RANSLATOR
T
E
E
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PDF 
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